![]() ![]() Of the four block(lines) in a set containing 32 bytes. Design a 4-way set associative cache with each a) The instruction set for a computer uses 28-bit addresses, with eachĪddressable unit being a byte. The cache memory recited in claim 16, wherein said memory comprises a RAM.1. G06F12/0842- Multiuser, multiprocessor or multiprocessing cache systems for multiprocessing or multitaskingĢ0.G06F12/0806- Multiuser, multiprocessor or multiprocessing cache systems.caches using pseudo-associative means, e.g. G06F12/0864- Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g.G06F12/0802- Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g.G06F12/08- Addressing or allocation Relocation in hierarchically structured memory systems, e.g.G06F12/02- Addressing or allocation Relocation.G06F12/00- Accessing, addressing or allocating within memory systems or architectures.G06- COMPUTING CALCULATING OR COUNTING.238000006731 degradation reaction Methods 0.000 description 2.230000015556 catabolic process Effects 0.000 description 2.230000000875 corresponding Effects 0.000 claims description 14.230000015654 memory Effects 0.000 claims abstract description 206.Application granted granted Critical Publication of US5694567A publication Critical patent/US5694567A/en Anticipated expiration legal-status Critical Status Expired - Lifetime legal-status Critical Current Links Assignors: BOUREKAS, PHILIP A., NG, ANDREW P. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). reassignment INTEGRATED DEVICE TECHNOLOGY, INC. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.) Filing date Publication date Application filed by Integrated Device Technology Inc filed Critical Integrated Device Technology Inc Priority to US08/386,025 priority Critical patent/US5694567A/en Assigned to INTEGRATED DEVICE TECHNOLOGY, INC. ![]() Original Assignee Integrated Device Technology Inc Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.) Ng Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.) Expired - Lifetime Application number US08/386,025 Inventor Philip A. Google Patents Direct-mapped cache with cache locking allowing expanded contiguous memory storage by swapping one or more tag bits with one or more index bitsĭownload PDF Info Publication number US5694567A US5694567A US08/386,025 US38602595A US5694567A US 5694567 A US5694567 A US 5694567A US 38602595 A US38602595 A US 38602595A US 5694567 A US5694567 A US 5694567A Authority US United States Prior art keywords signal cache address tag memory Prior art date Legal status (The legal status is an assumption and is not a legal conclusion. ![]() Google Patents US5694567A - Direct-mapped cache with cache locking allowing expanded contiguous memory storage by swapping one or more tag bits with one or more index bits US5694567A - Direct-mapped cache with cache locking allowing expanded contiguous memory storage by swapping one or more tag bits with one or more index bits
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